Mathematical modelling of a sPLL (spiking Phase-Locked Loop)
Type and duration:
Master project.
Context:
A phase-locked loop (PLL) is an input-output system that relates the phase of the output with that of the input in some desired way. There exist several types of PLLs and their applications have been extremely broad. Recently, a new type of PLL has been envisioned: the spiking PLL (sPLL), which plays a fundamental role in the development of innovative Neuromorphic Devices. The aim of the project is to develop a mathematical model, based on ODEs, of an sPLL, which can further be used to aid in the design of neuromorphic devices. This project is in collaboration with the Dynamical Systems, Geometry and Mathematical Physics (DSGMP) research group.
Required skills:
Familiarity with ODEs and some experience with modeling, knowledge of a programming language such as Python and/or Matlab, and interest in Neuromorphic Circuits.
Contact person:
| Last modified: | 05 October 2021 2.34 p.m. |